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ESC India was specifically created for embedded systems engineers and technical managers who are actively seeking to upgrade their design expertise, knowledge and skills, as well as provide answers to their design challenges.
ESC India 2009 will be the one place where you can be assured of reaching these decision makers and designers driving India's fast-growing embedded systems design developments.
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 Definition: SystemC is often thought of as a hardware description language like VHDL and Verilog, but is more aptly described as a system description language, since it exhibits its real power during transaction-level modeling and behavioral modeling.
SystemC is a set of library routines and macros implemented in C++, which makes it possible to simulate concurrent processes, each described by ordinary C++ syntax.
Instantiated in the SystemC framework, the objects described in this manner may communicate in a simulated real-time environment, using signals of all the datatypes offered by C++, some additional ones offered by the SystemC library, as well as user defined.
The behaviours (processes) defined may be instantiated any number of times, and provisions are made for processes defined by hierarchies of other processes, as one would expect.
The language thus offered has semantical similarities to VHDL and Verilog, but may be said to have a syntactical overhead compared to these.
On the other hand, greater freedom of expressiveness is offered in return, like object oriented design partitioning and template classes.
Which is more: SystemC is both a description language and a simulation kernel.
The code written will compile together with the library's simulation kernel to give an executable that behaves like the described model when it is run. The performance of this simulation kernel is not to be compared with that of commercial VHDL/Verilog simulators designed to simulate RTL level designs at the present.
Source: Wikipedia (http://en.wikipedia.org/wiki/Systemc)
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