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company
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Formal Sciences Inc.
Formal Sciences Inc markets front end design tools to enable Formal Thinking in design/validation flow and hence improve productivity of design/validation engineers. These tools can be used to formally capture the design as micro-architecture models at a higher level of abstraction than RTL. System Verilog or Verilog or VHDL or C or C++ or System C codes can be automatically generated or the user can choose to code the design manually
http://www.formalsciences.com/
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