webinar

Combining Legacy FPGA and CPLD Designs to Create a New Xilinx Virtex-5 Design
Few engineers have the luxury of creating their Virtex-5 designs from scratch; typically they reuse HDL code written earlier or even schematics that were archived with some legacy designs. Incorporating old sources into a new design is only a half of the problem: things get complicated when old code has to be analyzed and modified. This webinar will provide an overview of Virtex-5 Technology and
http://www.aldec.com/Products/Evaluation.aspx?productevaluationid=8831f160-d0b5-4390-add7-0458b3b...

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• fpga : pld
• fpga : webinars

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webinar

Actel & Aldec: Innovative Reprogrammable Prototyping for Actel RTAX Space-Flight FPGA Designs
Designers working on Actel RTAX projects know that even the most advanced simulation models do not fully reflect the behavior of real hardware. Any design errors not showing in simulation can be extremely costly if you catch them after programming RTAX device. While existing prototyping solutions use disposable, one-time programmable devices, Aldec innovative prototyping solutions use reprogrammable flash-based devices and auxiliary...
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new product

Aldec and SynthWorks deliver Randomization and Functional Coverage Capabilities…
Aldec, Inc., in collaboration with SynthWorks Design Inc., today announces the availability of Open Source - VHDL Verification Methodology (OS-VVM™), underscoring the partnership’s commitment to provide continued support to the VHDL design community. OS-VVM delivers advanced verification test methodologies, including Constrained and Coverage-driven Randomization, as well as Functional Coverage, providing advanced features to VHDL design...
http://www.aldec.com/en/company/news/2012-01-09/100

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• fpga : news
• fpga : vhdl

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webinar

Aldec® and Doulos®: Migrating to Transaction-Level Modeling in SystemC
SystemC is a mature modeling language for electronic systems. Since 2001, SystemC has offered a standard solution for building reference models for the purposes of system validation and functional verification, complementing the use of VHDL or Verilog for hardware design. More recently, SystemC has provided the foundation for the TLM-2.0 standard, which addresses the Transaction-Level Modeling of virtual platforms for software development...
http://www.aldec.com/Products/Evaluation.aspx?productevaluationid=c6cc81a9-f8f1-41a5-91ee-f8407c5...

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• chip design : systemc
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company

Aldec Inc.
Aldec(r) Corporation, established in 1984, is an industry-leader in RTL Simulation and Electronic Design Automation (EDA). Aldec is committed to delivering performance verification products with the best ROI for Government, Military/Aerospace Telecommunications, Consumer Products and Wireless markets. Aldec offers a patented technology suite including: RTL Design, RTL Simulators, Design Rule Checking, In-circuit Logic Emulators,...
http://www.aldec.com/

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tutorial

Aldec Tutorials - SystemC, VHDL, Verilog
SystemC-Primer 1.1. HDL / VHDL Tutorials. Evita-VHDL interactive primer. ATP-Verilog 4.6 - Advanced Testing Package Tool. ATP-VHDL 4.6. Advanced Testing Package Tool, designed to test an engineer's competency with the VHDL langauge. Riviera 2007.06 - Powerful, high performance ASIC and High Density FPGA verification environment. Active-HDL 7.2sp2 - Completely integrated FPGA design entry and verification environment for VHDL, Verilog,...
http://www.aldec.com/downloads/

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new product

Aldec Takes FPGA & ASIC Debugging to the Next Level
Aldec, Inc. has launched the latest version of its high-performance, mixed-language verification tool, Riviera-PRO™. Unveiled at the Design Automation and Test in Europe (DATE) conference, Riviera-PRO release version 2012.02 supports a number of advanced verification methodologies which are set to greatly benefit the designers of complex FPGAs and those migrating to ASIC. New to version 2012.02 of Riviera-PRO are support for the...
http://www.aldec.com/en/company/news/2012-03-12/106

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