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webinar
 Debugging High Speed Memory and Serial buses with Greater System Visibility
System integration and validation has become more challenging due to greater levels of sophistication and complexity in modern mixed signal designs.
This live webinar will focus on the latest tools and techniques for properly verifying analog and digital characteristics of high performance designs.
In-depth applications examples will be covered including FPGA debug, high speed serial links and DDR memory testing.
Attend this 45 minute...
preview:
http://www.eetimes.com
9/8/2010
Tags: memory, webinars
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