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 Signs - VHDL Hardware DevelopementSigns is a development environment for hardware designs in VHDL and other hardware description languages. The tackled tasks are compilation, synthesis, simulation and testing of designs. Due to the integration of these main areas it provides the ability to debug designs in an all-embracing manner by switching between source code, netlist and simulation. Signs is free software and a protectionist of the open source spirit. Thereby it is...
 preview: http://www.iti.uni-stuttgart.de/~bartscgr/signs/wiki/index.php/Main_Page 10/23/2007Tags: vhdl
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