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 Is SystemVerilog Only for System-Level DesignSystemVerilog is not a completely new hardware description language (HDL). With its rich set of extensions to the existing Verilog HDL, SystemVerilog is fully backward compliant with Verilog. Many of these extensions to Verilog make it easier to create accurate, synthesizable models of designs of any size. These extensions also make SystemVerilog easier to use and are truly beneficial to every engineer currently working with Verilog.
 preview: http://www.mentor.com/products/fpga_pld/techpubs/mentorpaper_31255.cfm 4/10/2007Tags: systemverilog, vhdl
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