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paper
 VHDL and Verilog Compared and Contrasted Plus Modeled Example
This tutorial is in two parts.
The first part takes an unbiased view of VHDL and Verilog by comparing their similarities and contrasting their diffrences.
The second part contains a worked example of a model that computes the Greatest Common Divisor (GCD) of two numbers.
The GCD is modeled at the algorithmic level in VHDL, Verilog and for comparison purposes, C. It is then shown modeled at the RTL in VHDL and Verilog.
preview:
http://www.angelfire.com/in/rajesh52/verilogvhdl.html
8/5/2000
Tags: verilog, vhdl
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