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book
 SystemVerilog for Verification: A Guide to Learning the Testbench Language Features
Teaches the reader how to use the power of the new SystemVerilog testbench constructs plus methodology without requiring in-depth knowledge of Object Oriented Programming or Constrained Random Testing.
The book covers the SystemVerilog verification constructs such as classes, program blocks, C interface, randomization, and functional coverage.
SystemVerilog for Verification also reviews some design topics such as interfaces and array types....
preview:
http://www.amazon.com
6/6/2007
Tags: verification, verilog
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