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book
 System Verilog for Verification
The SystemVerilog for Verification book is a follow-on to the SystemVerilog for Design book, published earlier this year.
The book will introduce the reader to the advanced testbench, verification and programming features of the Accellera SystemVerilog 3.1a standard, focusing on how these constructs can be used to set up effective verification methodologies.
Readers should have a working knowledge of the Verilog HDL and preferably have read...
preview:
http://www.amazon.com
8/21/2006
Tags: verilog
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