Mixed-Signal Modeling with Vanilla VHDL and Verilog
This paper compares and contrasts mixed-signal modeling using hardware description languages with and without the analog and mixed-signal extensions.
We argue that there are several major advantages to performing mixed-signal modeling using VHDL and Verilog without the AMS extensions.
We refer to this style of modeling as vanilla HDL mixed-signal modeling.
Examples of vanilla mixed-signal codec models for both VHDL and Verilog are presented.
preview:
http://www.bluepc.com/mixpap.html
9/27/2002
