HDLmaker is a tool for generating Verilog designs.
HDLmaker simplifies the development of complex FPGA designs as well as PC Boards by performing the following tasks: Writes hierarchical Verilog code Generates retargetable IO pad rings Generates all of the necessary scripts and Make files Supports mulitlanguage projects Converts PCB net lists into VHDL and Verilog Generates SCALD and PADS PCB board netlists Generates...
preview:
http://www.polybus.com/hdlmaker/users_guide/
10/28/2005
