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personal page
 Janick Bergeron Personal Page
I have recently completed a book on how to write testbenches using Verilog or VHDL.
It describes the techniques that I have developed during my career as a Design Verification Engineer.
I still use them today.
Has a nice set of LINKS on Verification issues.
The Verification Guild is a moderated mailing list where verification professionals can discuss any issues and challenges presented by this most difficult task.
preview:
http://www.janick.bergeron.com/
12/23/2003
Tags: verification
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