Creating Assertion-Based Verification IP (Series on Integrated Circuits and Systems)
This book well present formal testplanning guidelines with examples focused on creating assertion-based verification IP. Note that there are many books published on assertion languages (such as SystemVerilog assertions and PSL). Yet, none of the discuss the important process of testplanning and using these languages to create verification IP. This will be the first book published on this subject
preview:
http://www.amazon.com
8/11/2006
