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paper
 An ESL Methodology for Functional Verification between Untimed C++ and RTL using SystemC
Many RTL designs are developed from C++ algorithms that have been extensively tested using a C++ testbench.
The C++ testbench often represents a huge engineering effort to provide as much coverage of the algorithm as possible.
Once the algorithm has been synthesized to RTL, however, a new testbench is typically written instead of using the original C++ testbench.
This creates a discontinuity between the verification performed on the...
preview:
http://www.mentor.com/products/esl/techpubs/mentorpaper_31761.cfm
4/10/2007
Tags: c, eda, systemc, verification
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