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paper
 A Loosely Coupled C/Verilog Environment for System Level Verification
In this paper, we present a software C-Verilog interface, which is designed for the functional verification of any type of large system design.
As a company specializing in ASIC verification, working with a wide range of systems including routers, parallel processors, and video applications, we not only developed this tool, but we are actively using it in large development environments with a variety of systems.
preview:
http://www.zaiqtech.com/innovation/wp_verilog.html
8/29/2002
Tags: verification
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