Aldec® and Doulos®: Migrating to Transaction-Level Modeling in SystemC
SystemC is a mature modeling language for electronic systems.
Since 2001, SystemC has offered a standard solution for building reference models for the purposes of system validation and functional verification, complementing the use of VHDL or Verilog for hardware design.
More recently, SystemC has provided the foundation for the TLM-2.0 standard, which addresses the Transaction-Level Modeling of virtual platforms for software development...
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