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project
 BYU JHDL, Open Source FPGA CAD Tools
JHDL is a set of FPGA CAD tools developed at Brigham Young University's Configurable Computing Laboratory that allows the user to design the structure and layout of a circuit, debug the circuit in simulation, netlist and interface for bit-stream synthesis, and so forth.
It is an exploratory attempt to identify the key features and functionality of good FPGA tools.
preview:
http://www.jhdl.org/
07/24/2003
Tags: fpga
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