FIR Filter Fits in an FPGA using a Bit Serial Approach
In this paper, I have shown that it is possible to pack a relatively complex digital signal processing function into an FPGA by using bit serial structures.
The cost of bit serial architectures in terms of more clock cycles can be offset to some degree by the shorter delay paths between pipeline registers.
The resulting design is fast enough for many applications where a bit serial process may not have been considered.
preview:
http://www.andraka.com/files/fir.pdf
10/13/2003
