Design and Implementation of an Ordered Memory Access Architecture
This paper describes a multiprocessor machine for real-time Digital Signal Processing that uses commercial programmable DSP chips.
The architecture is a shared memory, single shared bus parallel processor designed to run signal processing tasks that can be statically scheduled.
The paper is in PDF format.
preview:
http://ptolemy.eecs.berkeley.edu/publications/papers/93/OMA_ICASSP93/
5/14/2000
