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paper
 Using JTAG Emulation for Board-Level Functional Test
As chip packaging and interconnects become more dense and operate at higher clock frequencies, physical access for traditional bed-of-nails testing becomes limited.
These results in loss of ICT (in-circuit test) fault coverage and higher test fixture costs.
Reduced fault coverage, coupled with limited diagnostic resolution at ICT and FT (functional test), often add up to excessive debug times in ICT/FT repair stations.
These costly,...
preview:
http://www.corelis.com/products/white_papers/ScanExpress_JET_White_Paper.pdf
9/29/2008
Tags: debugger
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