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core
 The JAM CPU - A CPU core in VHDL
The JAM CPU is a 32bit 5 stage pipelined RISC core with forwarding and hazard handling.
Its basic design is derived from the DLX architecture (from the Patterson & Hennessy books). The JAM CPU core is implemented in VHDL and has been tested in an actual FPGA (the Xilinx Virtex chip). We have released our CPU core under the GNU Lesser General Public License (LGPL) in the hope that it will be useful for people studying VHDL or computer...
preview:
http://www.digitalfanatics.org
9/11/2008
Tags: cores
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