SEO Training
Even in hi-tech, getting your company to the top of Google is important. Also using Social Media Marketing! Learn how!

e-clips news alerts by keyword

by jason mcdonald, senior editor | read other blog posts

Blog and news analysis from the recent PCI SIG developers conference. PCI Express 3.0 was the hot, new thing, especially among IP (intellectual property) vendors. But for most developers of embedded systems, PCI 2.1 is where the action is at.

contents of this post:

1. pci express 3.0 - eda, intellectual property and the cutting edge
2. pci express 3.0 - news you can use
3. pci express - the trailing edge
4. feedback - read it
5. feedback - give it

pci express 3.0 - eda, intellectual property and the cutting edge

For most technologists - especially journalists - it's all about the future, all the time. The great waves of PCI deployment, and the subsequent waves of PCI Express (PCIe, for short), have also convinced many that each wave will be bigger and better than the next. The victory of PCI Express is no doubt assured - with competing I/O standards pushed to the margins and niche markets.

I was lucky enough to attend the PCI SIG 's recent Development Forum in Santa Clara, California, July 15, 2009. Although most embedded developers are not yet deploying PCI Express 2.0, much less 3.0, the news buzz was definitely about the forthcoming 3.0 roll out. Al Yanes, President and Chairman of the SIG, presented a roadmap for the 3.0 rollout, which is not yet published on the SIG website. Here are some of the bullet points -

• PCIe 3.0 is the next evolution of the ubiquitous and general-purpose PCI Express I/O Standard. At 8GT/s bit rate, the interconnect performance will double over PCIe 2.0.
• Backward compatibility with previous PCIe standards will be preserved.
• The PCIe 2.0 bit rate is specified at 5GT/s. However, with the 20% performance overhead of the 8b/10b encoding scheme, the delivered bandwidth is actually 4Gb/s. PCIe 3.0 removes the requirement for 8b/10b encoding and uses scrambling with a new 128b/130b encoding scheme instead which has neglible overhead. This scheme change allows for 8GT/s to be achieved.
• PCIe 3.0 specifications will be available throughout 2009, with shipping product available in 2010.

pci express 3.0 - news you can use

It's still early for PCIe 3.0, but like sharks after blood or bees after honey, some of the cutting edge vendors are beginning to deploy products that assist in PCIe 3.0 designs. Synopsys, for example, announced its complete DesignWare® IP solution for PCI Express® (PCIe®) 3.0 consisting of digital controllers, PHY and verification IP. PCI Express 3.0 is the next generation of the PCI Express I/O standard, which is currently under development within the PCI Special Interest Group (PCI-SIG®) at a preliminary revision 0.5. Synopsys' high-quality DesignWare IP enables easy integration of the 8.0 GT/s PCI Express 3.0 interface into system-on-chips (SoCs) for high-performance enterprise computing applications.

Similarly, Gennum Corporation (TSX: GND) announced that its Snowbush IP group has developed the industry’s first available integrated PCI Express® 3.0 (Gen 3) PHY and Controller IP solution. The new PCIe® 3.0 cores can be licensed immediately by system-on-a-chip (SoC) and system companies, enabling early deployment of PCIe 3.0 (Gen 3) in systems requiring the 8.0 Gigatransfers per second (GT/s) performance of this new PCI-SIG standard. PCIe 3.0 opens up more bandwidth using the same physical connectors and adds new features to improve the user experience in server network and computer products using PCI Express.

You can follow the PCI Express news via eg3.com as it develops, here .

pci express - the trailing edge

For most embedded systems developers, however, one eye on PCIe 3.0 is sufficient. That is our future, but it isn't here yet and probably won't arrive until 2011 in real deployments outside of graphics and PC's, the traditional "early adopters" of new higher performance I/O. That said, PCIe 2.0 and 2.1 are where the action is now as these standards migrate into embedded. In fact, if there were a true embedded show for PCIe, it would be all about 2.0 / 2.1 in terms of deployment.

The best website to begin with in terms of standards is, of course, that of the SIG, here . They have press releases, standards, etc., but primarily for member companies. Another choice is the Intel website for PCI Express, where you can find Intel information, although it is primarily PC-centric. Other vendors like Mellanox, National Instruments, and PLX have written some key white papers on PCIe. You can find links to all those on the eg3.com, PCI Express keyword page.

Finally, a heads up on an intriguing topic in the PCIe domain - I/O Virtualization. According to the PCI SIG:

PCI-SIG I/O Virtualization (IOV) Specifications, in conjunction with system virtualization technologies, allow multiple operating systems running simultaneously within a single computer to natively share PCI Express® devices. These specifications are grouped into three areas:
• Address Translation Services (ATS): this specification provides a set of transactions for PCI Express components to exchange and use translated addresses in support of native I/O Virtualization.
• Single Root IOV: this specification provides native I/O Virtualization in existing PCI Express topologies where there is a single root complex.
• Multi-Root IOV: this specification builds on the Single Root IOV Specification to provide native I/O Virtualization in new topologies (such as blade servers) where multiple root complexes share a PCI Express hierarchy.

You can take an on-demand webinar on the topic, here .

feedback - read it:

feedback - give it:

	submit feedback to this blog post your name: your company (optional): your e-mail (optional): (Email will not be published!) please type your comment below, and hit send: IMPORTANT: to prevent spam, please re-type the letters that you read in this graphic: * graphic says:

Express Logic develops, markets and supports the ThreadX® real-time operating system (RTOS), NetX™ TCP/IP networking stack, USBX™ USB stack, and FileX® embedded file system, and PrismX™ GUI toolkit for embedded applications. ThreadX is a royalty-free, full source code, small-footprint, low-overhead RTOS that is extremely easy to learn and use. ThreadX is one of the most widely deployed RTOS products in the world, with over 800 million products based on ThreadX.