Innovative Integration
Innovative Integration provides board-level hardware products that integrate the best analog I/O and reconfigurable FPGAs to provide cost-effective solutions for challenging data acquisition and signal processing applications.
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Alliance - a free VLSI CAD System
Alliance is a complete set of free CAD tools and portable libraries for VLSI design.
It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools.
Advanced verification tools for functional abstraction and static timing analysis are part of the system.
A complete set of portable CMOS libraries is provided, including a RAM generator, a ROM generator and a data-path compiler.
preview:
http://www-asim.lip6.fr
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FreeHDL project
Project goals: To develop a VHDL simulator that: Has a graphical waveform viewer.
Has a source level debugger.
Is VHDL-93 compliant.
Is of commercial quality. (on par with, say, V-System - it'll take us a while to get there, but that should be our aim) Is freely distributable - both source and binaries - like Linux itself. (Under the Gnu General Public License (GPL)). Works with Linux.
If others want to port it to other...
preview:
http://www.freehdl.seul.org
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Hamster - High performance AMS Tool for Engineering and Research
hAMSter provides a powerful PC-based solution for modeling and simulation with VHDL-AMS. hAMSter -the high performance AMS tool for engineering and research-offers an easy-to-use, WINDOWS based alternative for a fast and efficient VHDL-AMS model development.
hAMSter is intended for all, who want to work on VHDL-AMS without a large design environment, for education and research and quick simulaton results.
preview:
http://www.hamster-ams.com
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SAVANT: An Extensible Intermediate for VHDL
The SAVANT project is an effort by University of Cincinnati's Experimental Computing Laboratory to build an extensible, object-oriented intermediate form (IIR) for the hardware description language VHDL.
The project produced a suite of software to analyze VHDL, build the IIR, and output C++ suitable for execution with the TyVIS VHDL simulation kernel.
preview:
http://www.ececs.uc.edu
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Signs - VHDL Hardware Developement
Signs is a development environment for hardware designs in VHDL and other hardware description languages.
The tackled tasks are compilation, synthesis, simulation and testing of designs.
Due to the integration of these main areas it provides the ability to debug designs in an all-embracing manner by switching between source code, netlist and simulation.
Signs is free software and a protectionist of the open source spirit.
Thereby it is...
preview:
http://www.iti.uni-stuttgart.de
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