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Covered Project
Covered is a Verilog code coverage analysis tool that can be useful for determining how well a diagnostic test suite is covering the design under test. Typically in the design verification work flow, a design verification engineer will develop a self-checking test suite to verify design elements/functions specified by a design's specification document.
preview: http://covered.sourceforge.net   |

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Eclipse Verilog editor
Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.
preview: http://sourceforge.net   |

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Hot PLI Stuff
The Programming Language Interface is a way to extend the functionality of Verilog simulators. Why try to build every possible feature into a tool? The PLI lets you add your own custom applications such as C models, delay calculators, file I/O, and more.
preview: http://chris.spear.net   |

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Source Navigator for Verilog
Source Navigator for Verilog is full featured tool for editing and navigating through large projects with many verilog files. It parses verilog code into a database that can be used to navigate files, trace connectivity, and find modules and signals in the design. It can even parse your files as you edit so you don't launch those long compile scripts only to end up with a syntax error after 5 minutes of compiling.
preview: http://snverilog.sourceforge.net   |

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Verilog2C++
Verilog2C++ is a Verilog to C++ translation program. Introduction Verilog2C++ translates a C++ class of a Verilog design using a cycle-accurate representation of each nets and registers. Verilog2C++ is about 10 times faster than other commercial simulators, but has only simple functions. Verilog2C++ charcteristics Support for IEEE1364-2001 Only two sate simulation Static scheduled and cycle based simulation
preview: http://verilog2cpp.sourceforge.net   |