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paper    

Executive Presentation - Meeting the Critical Challenges of IC Implementation
At the 2008 Design Automation Conference in June, Joseph Sawicki, vice president and general manager of the Design to Silicon Division, laid out Mentor’s strategy to help customers with the challenges they face with IC implementation as they move to smaller process nodes. Sawicki discusses new technology acquisitions and developments, product enhancements, and organizational alignment. He also describes how Mentor is driving toward the...
preview: http://www.mentor.com  

paper    

Mixed-Signal Modeling with Vanilla VHDL and Verilog
This paper compares and contrasts mixed-signal modeling using hardware description languages with and without the analog and mixed-signal extensions. We argue that there are several major advantages to performing mixed-signal modeling using VHDL and Verilog without the AMS extensions. We refer to this style of modeling as vanilla HDL mixed-signal modeling. Examples of vanilla mixed-signal codec models for both VHDL and Verilog are presented.
preview: http://www.bluepc.com  

paper    

VHDL and Verilog Compared and Contrasted Plus Modeled Example
This tutorial is in two parts. The first part takes an unbiased view of VHDL and Verilog by comparing their similarities and contrasting their diffrences. The second part contains a worked example of a model that computes the Greatest Common Divisor (GCD) of two numbers. The GCD is modeled at the algorithmic level in VHDL, Verilog and for comparison purposes, C. It is then shown modeled at the RTL in VHDL and Verilog.
preview: http://www.angelfire.com  

hot list    

EDA Industry Working Groups
The Electronic Design Automation (EDA) and Electronic Computer-Aided Design (ECAD) one-stop standards resource. SystemVerilog : 3.0 LRM 3.1 LRM Basic and Design Committee Testbench and Enhancements C Interface Assertion. VHDL links
preview: http://www.eda.org  

hot list    

Verilog
Hot links for Verilog Docs and Tutorials, Free Tools, Vendors, Magazines and Books.
preview: http://www.verilog.net  

portal    

Project Veripage
Project VeriPage started in 1997 as a community driven resource center for free and timely information on Verilog HDL and Verilog PLI. At that time, any information on these suvjects were scare, let alone free. Very soon, Project VeriPage became the main resource for these information on the web, as recognized by prestigious web directories such as Yahoo! (only entry under Verilog general category) and search engines such as Google (the...
preview: http://www.project-veripage.com  

ide    

Verilog IDE
vIDE (which stands for Verilog IDE) is a fully featured, cross-platform, integrated environment for designing, testing and debugging Verilog applications. It aims to full OVI compliance.
preview: http://sourceforge.net