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Ease Trial Download
EASE offers the best of both worlds with your choice of graphical or text based HDL entry. You don’t need to be a master of either Verilog or VHDL. When you're creating a new design, just enter your design using your mix of graphics and text. EASE automatically generates optimized HDL code for you in the selected language - VHDL or Verilog.
preview: http://www.hdlworks.com   |

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freeware EDA
These pages provide links to people working on freeware EDA tools, and is the home page for a Freeware Verilog,VHDL and Analog Mixed Signal project (a.k.a. the V-2000 project, still in its infancy).
preview: http://www.v-ms.com   |

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GOF - Gates on the Fly - Verilog Tool
GOF, Gates On the Fly, is a graphical tool specialized in verilog netlist debug and modification. It allows users to process netlist in GUI mode. In IC Design flow, the traditional way to edit or debug netlist is a manual process or with some help of script tools like perl or tcl. The manual process is error prone and tedious. When it comes to SOC design with multi-million-gate size, the netlist processing is even harder and more complicate.
preview: http://www.nandigits.com   |

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OVM - Open Verification World
Welcome to OVM World The OVM is based on the IEEE 1800 SystemVerilog standard and supports design and verification engineers developing advanced verification environments that offer higher levels of integration and portability of Verification IP. The methodology is non-vendor specific and is interoperable with multiple languages and simulators. The OVM is fully open, and includes a robust class library and source code that is available for...
preview: http://www.ovmworld.org   |

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