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association    

Accellera
Accellera is a non-profit organization that drives worldwide development and use of standards required by systems, semiconductor, and design tools companies that enhance a language-based design automation process. Accellera provides design standards for quick availability and use in the electronics industry. The organization's members cooperatively deliver much-needed EDA standards that lower the cost of designing commercial IC and EDA products.
preview: http://www.accellera.org  

software    

v2html
v2html is a free perl script that converts verilog designs into webpages. Once converted the webpages can be opened directly in a browser (using File->Open), or placed on a webserver. The webpages contain: The verilog with colour coded keywords, comments, signals etc. The colour coding lets you see at a glance whether a signal is an input, output, wire or register. Links where modules, functions, tasks, defines, parameters etc. are used...
preview: http://www.burbleland.com  

podcast    

Aldec's New RTL (Mixed Language) Simulator for the FPGA Market
Dave Rinehart, Vice President of Marketing at Aldec, discusses the 'gap' in the FPGA development tools space. Today, FPGA designers can purchase a high performance mixed language RTL simulator from Aldec or other commercial EDA vendors starting at $6,000 or alternatively purchase a restricted, single language, FPGA vendor supplied simulator for $1,000 or less. Dave discusses how Aldec's new product offer fills this market gap and provides...
preview: http://www.eg3.com   date: 7/14/2009

resource    

Verilog Resources
This web site is dedicated to Verilog in particular, and to Verifying Logic in general. To that end a collection of resources are available here; including an free editing mode for the verilog language; links to various books that are useful in understanding verilog, and verification in general; and links to same development tools.
preview: http://www.verilog.com  

service    

C-to-Verilog - Free Service
C-to-Verilog is a free service for circuit designers. We invite our visitors to create hardware circuits using the service provided here on our website. Users may submit their C programs and download a verilog module which can then be embedded on FPGAs. Our website will automatically synthesize the C program into a verilog module. For additional information on how to use our website, watch the screencast below.
preview: http://www.c-to-verilog.com  

archive    

Cliff Cummings Verilog and SystemVerilog White Papers
temVerilog Implicit Port Connections - Simulation & Synthesis * The IEEE Verilog-2001 Simulation Tool Scoreboard * Verilog-2001 Behavioral and Synthesis Enhancements * Verilog Nonblocking Assignments With Delays, Myths & Mysteries * The Fundamentals of Efficient Synthesizable Finite State Machine Design using NC-Verilog and BuildGates
preview: http://www.sunburst-design.com  

tool    

HDL Maker
HDLmaker is a tool for generating Verilog designs. HDLmaker simplifies the development of complex FPGA designs as well as PC Boards by performing the following tasks: Writes hierarchical Verilog code Generates retargetable IO pad rings Generates all of the necessary scripts and Make files Supports mulitlanguage projects Converts PCB net lists into VHDL and Verilog Generates SCALD and PADS PCB board netlists Generates...
preview: http://www.polybus.com