FPGA Tutorial: Free 'Insider's Guide' (2009 Edition)
Altera? Xilinx? FPGA boards or design tools as from Altium or Mentor Graphics? What do users and newbies think about new FPGA technologies? Find out in our free tutorial on FPGAs, tools, and boards.

Mocana NanoSSH - Embedded SSH Client and Server

tutorial    

Testbench.in - ASIC Functional Verification Tutorial
There are many sources available for basic VLSI/DIGITAL and Hardware Description Languages(HDL's). As the Verification becomes the more and more complex and important there is a need of Hardware Verification Languages (HVL's) like Systemverilog, OpenVera... etc and Methodologies. But there isn't any great source available for Hardware Verification Languages(HVL's) and Methodologies. What's on this site : We believe the best and easiest...
preview: http://www.testbench.in  

tutorial    

VHDL Verification Course
Verification is an important part of any ASIC design cycle. It's important that complex designs are simulated fully before prototypes are built, as it's difficult to find bugs in silicon and going through additional layout cycles is costly and time consuming. VHDL is well suited for verification. This course is an introduction to VHDL verification techniques. It assumes some familiarity with VHDL.
preview: http://www.stefanvhdl.com  

personal page    

Chris Spear's Verification World
Personal page with information on Verification, Verilog, PLI.
preview: http://chris.spear.net  

personal page    

Janick Bergeron Personal Page
I have recently completed a book on how to write testbenches using Verilog or VHDL. It describes the techniques that I have developed during my career as a Design Verification Engineer. I still use them today. Has a nice set of LINKS on Verification issues. The Verification Guild is a moderated mailing list where verification professionals can discuss any issues and challenges presented by this most difficult task.
preview: http://www.janick.bergeron.com  

university    

CMU Model Checking
Model checking is a method for formally verifying finite-state concurrent systems. Specifications about the system are expressed as temporal logic formulas, and efficient symbolic algorithms are used to traverse the model defined by the system and check if the specification holds or not. Extremely large state-spaces can often be traversed in minutes.
preview: http://www.cs.cmu.edu  

resource    

Verification Central LLC
Verification Central is dedicated to ASIC verification. It was established in May 2001. The first product from Verification Central is the best selling book on ASIC verification 'The Art of Verification with Vera'.
preview: http://www.verificationcentral.com  

project    

Jove - Open Verification Environment for Java
Jove is a set of Java APIs and tools to enable Verilog hardware design verification using the Java programming language. It contains components that accomplish the following: Verilog simulator interaction (via PLI 2.0, aka VPI) standalone behavioral simulation (i.e. a discrete event simulator) thread and event synchronization design verification abstractions (e.g. clock-relative signal access, mailboxes, semaphores)...
preview: http://jove.sourceforge.net