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An ESL Methodology for Functional Verification between Untimed C++ and RTL using SystemC
Many RTL designs are developed from C++ algorithms that have been extensively tested using a C++ testbench. The C++ testbench often represents a huge engineering effort to provide as much coverage of the algorithm as possible. Once the algorithm has been synthesized to RTL, however, a new testbench is typically written instead of using the original C++ testbench. This creates a discontinuity between the verification performed on the...
preview: http://www.mentor.com  

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Creating a Consistent Verification Environment from Algorithm to RTL
Hardware implementations of DSP designs typically start out as algorithms modeled in tools like Matlab(tm). Such tools provide a natural representation of the algorithm and an extensive collection of building blocks used to analyze algorithm performance, both quantitatively (S/N, BER, quantization errors, etc) and qualitatively (spectrum displays, processed image viewing, etc). They can also provide a quantitative analysis of possible fixed...
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Executive Presentation - Meeting the Critical Challenges of IC Implementation
At the 2008 Design Automation Conference in June, Joseph Sawicki, vice president and general manager of the Design to Silicon Division, laid out Mentor’s strategy to help customers with the challenges they face with IC implementation as they move to smaller process nodes. Sawicki discusses new technology acquisitions and developments, product enhancements, and organizational alignment. He also describes how Mentor is driving toward the...
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Scoring with HDL Designer
Have you ever wondered about the quality of code you are writing or that you plan to reuse from another engineer? Many teams have codified their RTL coding experiences into style guides providing rules and guidelines for creating designs. Unfortunately, these guides are rarely used or remembered. What if you could set up a tool that reflected your style guide? What if that tool could automatically provide you with a score representing the...
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A Loosely Coupled C/Verilog Environment for System Level Verification
In this paper, we present a software C-Verilog interface, which is designed for the functional verification of any type of large system design. As a company specializing in ASIC verification, working with a wide range of systems including routers, parallel processors, and video applications, we not only developed this tool, but we are actively using it in large development environments with a variety of systems.
preview: http://www.zaiqtech.com  

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Kozio Technical White Papers
White Papers One Button Test Strategy for Volume Manufacturing View Abstract | Implement a one button PASS/FAIL circuit board test strategy in a single day! Kozio’s hardware validation test suite provides an integrated and automated solution delivering at-speed functional test running on the device under test (DUT) coupled with powerful test management software. The latest kDiagnostics™ Manufacturing Suite offering from Kozio allows...
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Methodology and code reuse in the verification of Telecommunication SOCs
Semiconductor chip manufacturers are experiencing a widespread boom, creating unprecedented growth and success opportunities for both start-up fabless semiconductor companies and well-established high-tech corporations. The telecommunication industry is a major consumer of semiconductor chips.
preview: http://www.zaiqtech.com