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Cool Verification . Com
Cool Verification Breaking your products so your customers won't have to. Thoughts on hardware verification, the EDA industry, and related topics from the perspective of a verification consultant. Subscribe to this blog's feed Enter your email address: Delivered by FeedBurner Recent Posts Check Out the New Verilab Website! Comments on Cooley's Verification Census More DATE 2007 Photos Posted Birds-of-a-Feather at DAC -...
preview: http://www.coolverification.com  

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The VLSI Home Page
A practical guide to VLSI design and verification.
preview: http://www.vlsihomepage.com  

webinar    

Finding the toughest bugs with 0-In Formal Verification Web Seminar
As designs get more complex, verification cycles increase dramatically while quality hangs in the balance. As a result, many companies are looking for a better methodology to help them achieve improved verification productivity, predictability and quality. This seminar explains how formal verification can most effectively be used alongside simulation to allow design and verification engineers to find more bugs, earlier in the design process.
preview: http://www.mentor.com   date: 1/27/2009

webinar    

Best Practices and Methods for Mixed-Signal Verification
Is mixed-signal verification a major bottleneck within your IC design and verification flow? Are you part of an analog/mixed-signal design team that is required to deliver a high-quality functional 'digital-ONLY' simulation net list to a digital verification organization as part of SoC verification? If you answered yes to the above questions, attend this webinar and learn how Cadence' Services can help you: * Reduce ris
preview: http://www.techonline.com   date: 11/18/2009

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e Functional Verification Working Group
The e Functional Verification Language Working Group (eWG) was formed to define a standard for the e language. The eWG is sponsored by the Design Automation Standards Committee (DASC), which is a body of the Computer Society focused on electronic design automation standards. All standards related activity in the IEEE is governed by the IEEE Standards Association (IEEE/SA).
preview: http://www.ieee1647.org  

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Vera Open Source Initiative
OpenVera as an open source hardware verification language. The initiative will benefit customers and the industry by fostering the growth and availability of tools and intellectual property (IP) around an open source language. More than thirty EDA, IP and system on a chip (SoC) design companies have endorsed OpenVera and the Vera Open Source Initiative.
preview: http://www.open-vera.com