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FPGA's 101 - Amazing New FPGA in Embedded Book

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article   1-5 star rating for this site  
Enabling better testing: Reprogrammable on-chip instrumentation
This extensive look underneath the hood at on-chip instrumentation shows how at-speed validation for SoCs can be greatly improved with the right visibility inside. Successfully testing and validating today’s sophisticated ASICs and FPGAs requires sophisticated solutions, especially tools that can provide advanced controls and views into the embedded system. In the past, some vendors relied almost exclusively on pre-silicon verification,...
Click here to preview in another window preview: http://www.embedded-computing.com   date: 11/9/2009 ULCLOGO |

article   1-5 star rating for this site  
Unraveling debug and design verification snags
Paul notes that with FPGAs taking on the role of much denser, more versatile embedded platforms, designers are seeking advanced controls and views into the embedded system.
Click here to preview in another window preview: http://www.dsp-fpga.com   date: 11/24/2009 ULCLOGO |

personal page   1-5 star rating for this site  
Chris Spear's Verification World
Personal page with information on Verification, Verilog, PLI.
Click here to preview in another window preview: http://chris.spear.net   |





personal page   1-5 star rating for this site  
Janick Bergeron Personal Page
I have recently completed a book on how to write testbenches using Verilog or VHDL. It describes the techniques that I have developed during my career as a Design Verification Engineer. I still use them today. Has a nice set of LINKS on Verification issues. The Verification Guild is a moderated mailing list where verification professionals can discuss any issues and challenges presented by this most difficult task.
Click here to preview in another window preview: http://www.janick.bergeron.com   |

university   1-5 star rating for this site  
CMU Model Checking
Model checking is a method for formally verifying finite-state concurrent systems. Specifications about the system are expressed as temporal logic formulas, and efficient symbolic algorithms are used to traverse the model defined by the system and check if the specification holds or not. Extremely large state-spaces can often be traversed in minutes.
Click here to preview in another window preview: http://www.cs.cmu.edu   |

podcast   1-5 star rating for this site  
Mentor Graphics EDA Training and Employment Resources for Unemployed Designers
Recently unemployed? Concerned about your EDA technical training? Christine Egli and Tom Floodeen of Mentor Graphics discuss how the company is reaching out to the EDA community to offer technical training in EDA (Electronic Design Automation) to 'displaced workers.' For those who qualify, the program is an excellent way to beef up your technical skills as well as to network with other EDA professionals seeking employment opportunities.
Click here to preview in another window preview: http://www.eg3.com   date: 3/24/2009 ULCLOGO |

resource   1-5 star rating for this site  
Verification Central LLC
Verification Central is dedicated to ASIC verification. It was established in May 2001. The first product from Verification Central is the best selling book on ASIC verification 'The Art of Verification with Vera'.
Click here to preview in another window preview: http://www.verificationcentral.com   |

Express Logic - RTOS, TCP/IP, USB Stack, File System, GUI


NetX® and NetX Duo are Express Logic's high-performance implementation of IPv4 and IPv6 TCP/IP protocol standards. Both are fully integrated with the ThreadX® RTOS (real-time operating system) and are available for all supported processors. NetX and NetX Duo have a unique Piconet™ architecture. Combined with a zero-copy API, it makes them a perfect fit for today's deeply embedded applications that require network connectivity.
Express Logic - RTOS, TCP/IP, USB Stack, File System, GUI


 

 

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