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Averant White Papers
Topics include: * Automatic Verification of Timing Exceptions * AMBA Compliance Checking using Static Functional Verification * ARM's Paper on X Analysis - Tech Committee Award, SNUG '03 * etc.
preview: http://www.averant.com   |

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Novas System-on-Chip White Papers
Transaction-based Debug of PCI Express Embedded SoC Platforms - presented at IPSoC * Transaction-Level Modelling and Debug of SoCs - presented at IPSoC *D Design and Debug with Advanced Languages: Challenges and Opportunities for SystemVerilog- presented at DVCon * Assertion-Based Hardware Debugging - presented at DVCon * Novas Debug Technology White Paper
preview: http://www.novas.com   |

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Zaiq's White Papers
A collection of white papers with topics surrounding verification. Topics include: * Evaluating and Improving Emulator Performance * Retargetable Transaction-Based System Level Verification * Methodology and Code Reuse in the Verification of SOCs * Verification of Skew and Jitter Tolerance and Compensation in High-Speed Interfaces...
preview: http://www.zaiqtech.com   |

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Mentor Graphics - Verification Academy
The Verification Academy provides a methodological bridge between high-level value propositions (related to advanced verification technology) and the low-level details (related to specific tool and verification language details). The Verification Academy, which features Harry Foster as the primary instructor, can be accessed around the clock. The Verification Academy provides...
preview: http://verification-academy.mentor.com   |

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Testbench.in - ASIC Functional Verification Tutorial
There are many sources available for basic VLSI/DIGITAL and Hardware Description Languages(HDL's). As the Verification becomes the more and more complex and important there is a need of Hardware Verification Languages (HVL's) like Systemverilog, OpenVera... etc and Methodologies. But there isn't any great source available for Hardware Verification Languages(HVL's) and Methodologies. What's on this site : We believe the best and easiest...
preview: http://www.testbench.in   |

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VHDL Verification Course
Verification is an important part of any ASIC design cycle. It's important that complex designs are simulated fully before prototypes are built, as it's difficult to find bugs in silicon and going through additional layout cycles is costly and time consuming. VHDL is well suited for verification. This course is an introduction to VHDL verification techniques. It assumes some familiarity with VHDL.
preview: http://www.stefanvhdl.com   |