
SHARC Processor Evaluation Kit Limited Time Offer
Analog Devices is offering a 50% discount on new SHARC Processor Family evaluation kits until July 31, 2008.
The SHARC Processor fits into a variety of applications such as Digital Home, Pro Audio, Industrial and Instrumentation, Automotive, Military, and Medical.
The following kits will be discounted to $249 through your local Distributor: ADZS-21262-EZLITE, ADZS-21364-EZLITE, ADZS-21369-EZLITE, and ADZS-21375-EZLITE.

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hot list
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Programmable Logic Device Resources
* Tutorials * FAQ * Newsgroups * Publicly Available Sites * 3rd Party Software Vendors * PLD Vendors * SOC Vendors
preview:
http://www.brunham.net
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organization
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NASA Office of Logic Design
Selected Papers 'A Comparison of Bus Architectures for Safety-Critical Embedded Systems,' John Rushby 'Apollo Spacecraft,' George Low, NASA MSC Office of Logic Design Seminars and Workshops 'Back to the Moon: The Verification of a Small Microprocessor's Logic Design' - (September 19, 2007) 'Engineering Aspects of the Lunar Orbiter Laser Altimeter (LOLA) Digital Unit Design' - (October 17, 2007) OLD Seminar Archive...
preview:
http://www.klabs.org
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sbc
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Leaper-48 Universal Hand-Held Device Programmer with USB I/F
The Leaper-48 is a Universal programmer for programming EPROMS, EEPROMS, Flash EPROMS, Serial E/EPROMS, NV RAM, Microcontrollers, DSPs, PLDs etc. Devices with a power supply voltage as low as 1.0V are supported.
The Leaper-48 is fitted with a 48 pin ZIF socket which accepts devices with a 200-600mil wide package.
The Leaper-48 is in stock ready for immediate shipment.
preview:
http://www.thedebugstore.com

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portal
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Programmable Logic DesignLine
Where can you find real solutionsto tough programable logic design challenges? The Programmable Logic DesignLine is the place.
This site provides the practical how-to information needed to program, develop, and implement field programmable gate arrays (FPGAs) and programmable logic devices (PLDs) in wireless, networking, industrial, automotive, and other design applications
preview:
http://www.pldesignline.com
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paper
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Getting Started with CPLDs
What is a CPLD? A CPLD is a combination of a fully programmable AND/OR array and a bank of macrocells.
The AND/OR array is reprogrammable and can perform a multitude of logic functions.
Macrocells are functional blocks that perform combinatorial or sequential logic, and also have the added flexibility for true or complement, along with varied feedback paths.
preview:
http://www.xilinx.com
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conference
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International Conference on Field Programmable Logica and Applications (FPL)
The International Conference on Field Programmable Logica and Applications (FPL) is the first and largest conference covering the rapidly growing area of field-programmable logic.
During the past 16 years, many of the advances achieved in reconfigurable architectures, applications, design methods and tools have been first published in the proceedings of the FPL conference series.
Its objective is to bring together researchers and industry...
preview:
http://ce.et.tudelft.nl
date: 8/27/2007
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seminar
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Paid Seminar': Understanding Programmable Logic Controllers
Mainly for end-users, but: During this three day session you will spend approximately 50% of the time actually working with various programmable controllers in a small group learning to program, connecting input/output devices, solving elementary and then more complex problems, and troubleshooting.
Approximately 50% of the time will be spent in lecture session . . . [Paid Tutorial - Various Locations, USA]
preview:
http://www.nttinc.com
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I/O Designer follows major FPGA vendor rules for correct I/O assignments.
It also eliminates re-spin risk, improves PCB performance, and reduces routing congestion.
View the free demo.
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