
MeshNetics - 802.15.4 / ZigBee Wireless RF Modules MeshNetics is a creator of easy-to-integrate 802.15.4 / ZigBee wireless RF modules and ZigBee PRO-certified mesh networking software, used by OEMs and system integrators to add wireless connectivity to their products and solutions.
MeshNetics RF modules feature industry-leading range performance, long battery life and ultra-small footprint.
They are designed for use in 868/915 MHz and 2.4 GHz frequency bands.
MeshNetics is a single source of ZigBee modules, development tools, networking software, technical support, and design services.

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webinar
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Add Mixed Technology, Including RF, to Your PCB Design in Half the Time
For complex mixed technology system designs with RF, analog, and digital technologies; the RF portion commonly takes up to 75% of the total design cycle.
At the same time, today's RF systems have increased in complexity to a point where these cycle times are measured in months rather than weeks or days.
Plus, design re-spins are common.
The PCB design community has lived with these issues for a long time and the situation increasingly...
preview:
http://www.mentor.com
date: 4/29/2008
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webinar
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Bridging the Gap between FPGA and PCB
Due to the increasing number of complex FPGA designs on PCB designs today it becomes a necessity that the common gap between the FPGA and PCB worlds is closed.
The FPGA constraints are not longer the only variables controlling the FPGA pin-out, it becomes a painful necessity to include the PCB requirements into this process in order to make a system that meets the overall system performance requirements.
preview:
http://www.mentor.com
date: 5/16/2007
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webinar
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S-Parameters: Are they as good as you think
S-parameters are one of the most common methods of modelling passive interconnects in high-speed SERDES designs.
In this one-hour webinar, we will look at S-parameters in detail and discuss some of the common issues that are found with S-parameters in simulation.
preview:
http://www.mentor.com
date: 10/10/2007
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webinar
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Technology, Topology & Termination: Fundamentals of High-Speed Design
As IC switching speeds continue their progressively-faster march, driven by advances in lithography, more and more digital designers have been faced with signal-integrity problems like over/undershoot, ringing, and glitching.
At the same time, progressively-faster clock speeds result in much less forgiving timing margins and additional consideration must be given to accommodate government radiated emissions standards.
During this 1-hour...
preview:
http://www.mentor.com
date: 1/10/2008
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webinar
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Add Mixed Technology, including RF, to your PCB Design in Half the Time
For complex mixed technology system designs with RF, analog, and digital technologies; the RF portion commonly takes up to 75% of the total design cycle.
At the same time, todays RF systems have increased in complexity to a point where these cycle times are measured in months rather than weeks or days.
Plus, design re-spins are common.
The PCB design community has lived with these issues for a long time and the situation increasingly...
preview:
https://event.on24.com
date: 4/29/2008
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webinar
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Agilent Medalist Bead Probe Technology - A Simple and Proven Test Solution
Sign up for our free webcast to learn how Agilent's latest innovation can dramatically improve in-circuit test coverage! Agilent Medalist Bead Probe Technology is an exciting new methodology for placing test points directly onto a PCB's copper traces.
These beads then serve as highly reliable test points for use during in-circuit testing.
This new innovation can significantly improve test access while providing superior test reliability...
preview:
http://www.techonline.com
date: 1/24/2007
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With PADS® I/O Designer, you can easily create legal FPGA pin assignmentsup to 50% times fasterwith its correct-by-construction, drag and drop functionality.
By reducing design cycle time, I/O Designer accelerates time to market, enabling your company to compete in the ever-changing electronics market.
I/O Designer follows major FPGA vendor rules for correct I/O assignments.
It also eliminates re-spin risk, improves PCB performance, and reduces routing congestion.
View the free demo.
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