
MeshNetics - 802.15.4 / ZigBee Wireless RF Modules MeshNetics is a creator of easy-to-integrate 802.15.4 / ZigBee wireless RF modules and ZigBee PRO-certified mesh networking software, used by OEMs and system integrators to add wireless connectivity to their products and solutions.
MeshNetics RF modules feature industry-leading range performance, long battery life and ultra-small footprint.
They are designed for use in 868/915 MHz and 2.4 GHz frequency bands.
MeshNetics is a single source of ZigBee modules, development tools, networking software, technical support, and design services.

| |
-
archive
-
Coware Technical Papers
Presented: January 2007 Using Tenison VTOC to Integrate RTL IP into CoWare High-Performance Virtual Platforms Written by: Dr. Jeremy Bennett, CTO, Tenison; Dr. Tim Kogel, Solution Specialist, CoWare Inc Presented: IP-based SoC Design Conference December 2006 Fast Virtual Prototyping for Early Software Design & Verification Written by: Amit Garg, CoWare, India Presented: DATE March 2006 Virtual Prototyping...
preview:
http://www.coware.com
-
archive
-
FS2 White Papers - SOC, FPGA, Debug & More
DesignCon 2004 Application Article 'Instrumentation-Based Analysis of System FPGAs' 02-04-04 DesignCon 2004 Presentation paper 'Multi-Core Embedded Debug for Structured ASIC Systems' 02-2-04 Electronic Design Article 'SoC Debug Environment Opens System-Level View' 02-2-04 EETimes Article 'First Silicon tackles multiprocessor debug on SoCs' 04-18-03 EETimes Article 'Method offers snapshot of SoC operation'
preview:
http://www.fs2.com
-
archive
-
White Papers by Celoxica
Topics include: * Computing in Reconfigurable Logic * Introducing Software Paradigms in Hardware Design * New Solutions for Reconfigurable Electronics * Real World Experiences Designing For Mixed CPU + FPGA Systems * etc.
preview:
http://www.celoxica.com
-
showcase
-
ADVance MS
As part of Mentor's Scalable Verification solution, the ADVance MS (ADMS) multi-language simulator extends traditional SoC functional verification methodology to the mixed-signal arena.
ADMS supports multiple industry-standard languages, including Verilog, VHDL, Verilog-AMS, VHDL-AMS, SPICE, C, SystemC, and SystemVerilog, providing an integrated verification environment enabling large design teams to validate and verify analog/mixed-signal designs throughout the design cycle.
preview:
http://www.mentor.com

 |
| 
| 
With PADS® I/O Designer, you can easily create legal FPGA pin assignmentsup to 50% times fasterwith its correct-by-construction, drag and drop functionality.
By reducing design cycle time, I/O Designer accelerates time to market, enabling your company to compete in the ever-changing electronics market.
I/O Designer follows major FPGA vendor rules for correct I/O assignments.
It also eliminates re-spin risk, improves PCB performance, and reduces routing congestion.
View the free demo.
| 
| 
|
|
|