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Choosing the right Multicore software architecture for high performance control and data-plane …
Multicore processors are being broadly adopted in networking applications in order to meet increasingly demanding performance requirements and tight power budgets. While multicore offers a continuation of Moore ’s law on the hardware side, it introduces a disruptive change and therefore a great challenge for software designers. In this webinar Enea will present an overview of various software architectures for control plane and data plane...
preview: https://event.on24.com   date: 11/17/2009 |

webinar    

Choosing the right Multicore software architecture for high performance control and data-plane …
Multicore processors are being broadly adopted in networking applications in order to meet increasingly demanding performance requirements and tight power budgets. While multicore offers a continuation of Moore ’s law on the hardware side, it introduces a disruptive change and therefore a great challenge for software designers. In this webinar Enea will present an overview of various software architectures for control plane and data plane...
preview: https://event.on24.com   date: 11/17/2009 |

webinar    

Conquering the Memory Bandwidth Bottleneck On-Chip
Memory bandwidth challenges are increasing with next-generation high-bandwidth technologies and designers are looking for new cost-effective approaches for resolving bandwidth and efficiency issues on-chip. Today's popular home entertainment and mobile devices require an increasing number of processors that are dependent on sharing the same pipe, which has generated a sizeable efficiency bottleneck for SoC designers and system architects....
preview: http://www.eetimes.com   date: 9/23/2010 |

webinar    

Debugging High Speed Memory and Serial buses with Greater System Visibility
System integration and validation has become more challenging due to greater levels of sophistication and complexity in modern mixed signal designs. This live webinar will focus on the latest tools and techniques for properly verifying analog and digital characteristics of high performance designs. In-depth applications examples will be covered including FPGA debug, high speed serial links and DDR memory testing. Attend this 45 minute...
preview: http://www.eetimes.com   date: 9/21/2010 |

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Designing Low Power SoCs for Multimedia and Cellular Baseband Applications
To meet the relentless demand for improved feature sets and functionality in today's advanced cellular baseband and multimedia chips, modern SoCs require more powerful processing capabilities than ever before. In the same breadth, these SoCs are expected to operate within the same power budget allocated to preceding, less complex chipsets, particularly for mobile applications. This CEVA webinar will deliver a fresh perspective on the...
preview: http://www.techonline.com   date: 10/14/2009 |

webinar    

EDA Virtual Conference- EDA: The Next Big Things
OpenSystems Media is proud to announce the first EDA Virtual Conference, entitled EDA: The Next Big Things. Engineers from around the world are invited to learn about Analog and Mixed Signal, System-on-Chip, High-Level Design, and Verification. Each session will also include a special 'Ask the Experts' panel for attendees to ask their questions and network with vendors. The fifth and final session of the day is the keynote Executive...
preview: https://event.on24.com   date: 10/14/2010 |

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