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Mentor Graphics - IC Design.

Mentor Graphics
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Mentor Graphics

 

 

webinar   1-5 star rating for this site  
Building a Configurable Gigabit Ethernet Subsystem for Complex System-0n-Chips
As networking in the home continues to integrate more devices requiring higher bandwidth, new generations of Ethernet designs are being incorporated into complex SoC subsystems. These bandwidth requirements are causing designers to rapidly migrate from Fast Ethernet to Gigabit Ethernet. To support these designs, a configurable and robust IP solution is needed to easily support the rapidly changing market demands.
Click here to preview in another window preview: http://www.techonline.com   date: 12/19/2007

webinar   1-5 star rating for this site   site recommendation - wow, cool, new
Carbon Design Systems Webinar - Fast, Accurate Analysis of Architectural Decisions
The complexity of modern System-on-Chip (SoC) designs is exposing the weaknesses of traditional system architecture design methodologies. Poor performance, short battery life and random deadlocks are just a few of the problems which can be seen when SoC architects are forced to rely on spreadsheets and back of the envelope calculations. Virtual platforms enable system architects to quickly and easily make design decisions and then, more...
Click here to preview in another window preview: http://tinyurl.com   date: 10/28/2008

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webinar   1-5 star rating for this site  
Co-simulation Enables Efficient Co-Design of WLAN Antenna and Circuitry
To better streamline the design of wireless appliances, co-simulation is essential in today's EDA tools. RF & Microwave engineers can enjoy such a capability when employing Agilent's Advanced Design System (ADS) with integrated system, circuit, and EM (2D & 3D) simulation solutions. This webcast illustrates the value of using a seamless co-simulation platform while exploring the co-design of a WLAN polarization diversity antenna with its...
Click here to preview in another window preview: http://www.techonline.com   date: 5/28/2008

webinar   1-5 star rating for this site  
Co-simulation with MATLAB®, Simulink®, and HDL Simulators
When implementing a complex design in an ASIC or FPGA, engineers must be satisfied that the hardware implementation will match the system specification. Whether your HDL is written from scratch, automatically generated code, previously-written IP, or a mix of the three, you can use the EDA co-simulation link products from the MathWorks to ensure design correctness. In this webinar you will learn how you can ensure that your HDL...
Click here to preview in another window preview: http://www.techonline.com   date: 12/6/2007

webinar   1-5 star rating for this site  
CodeSourcery Math Libraries for the Cell Broadband Engine
The Cell Broadband Engine (Cell/B.E.) excels at high performance computing applications especially in the arena of signal- and image-processing (SIP). The trend in the aerospace and defense industry is to migrate to common, off-the-shelf solutions. These trends, along with higher dense computing requirements in support of full situation awareness, drive the desire for an embedded Cell/B.E. software stack. The first part of this...
Click here to preview in another window preview: https://event.on24.com   date: 11/15/2007

webinar   1-5 star rating for this site  
CodeSourcery SIP Primitives for the Cell Broadband Engine
The Cell Broadband Engine (Cell/B.E.) excels at high performance computing applications especially in the arena of signal- and image-processing (SIP). The trend in the aerospace and defense industry is to migrate to common, off-the-shelf solutions. These trends, along with higher dense computing requirements in support of full situation awareness, drive the desire for an embedded Cell/B.E. software stack. The first part of this...
Click here to preview in another window preview: https://event.on24.com   date: 11/15/2007

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The eT-Kernel Multi-Core Edition is a real time operating system (RTOS) for next-generation embedded systems with multi-core. It supports multiple scheduling modes, including True SMP Mode (TSM) and Single Processor Mode (SPM) that provide optimal application throughput while keeping realtime determinism. eSOL's Multi-core ready RTOS
eSOL's Multi-core ready RTOS


 

 

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