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webinar    

Finding the toughest bugs with 0-In Formal Verification Web Seminar
As designs get more complex, verification cycles increase dramatically while quality hangs in the balance. As a result, many companies are looking for a better methodology to help them achieve improved verification productivity, predictability and quality. This seminar explains how formal verification can most effectively be used alongside simulation to allow design and verification engineers to find more bugs, earlier in the design process.
preview: http://www.mentor.com   date: 1/27/2009

webinar    

Aldec® and Doulos®: Migrating to Transaction-Level Modeling in SystemC
SystemC is a mature modeling language for electronic systems. Since 2001, SystemC has offered a standard solution for building reference models for the purposes of system validation and functional verification, complementing the use of VHDL or Verilog for hardware design. More recently, SystemC has provided the foundation for the TLM-2.0 standard, which addresses the Transaction-Level Modeling of virtual platforms for software development...
preview: http://www.aldec.com   date: 1/29/2009

webinar    

Best Practices and Methods for Mixed-Signal Verification
Is mixed-signal verification a major bottleneck within your IC design and verification flow? Are you part of an analog/mixed-signal design team that is required to deliver a high-quality functional 'digital-ONLY' simulation net list to a digital verification organization as part of SoC verification? If you answered yes to the above questions, attend this webinar and learn how Cadence' Services can help you: * Reduce ris
preview: http://www.techonline.com   date: 11/18/2009

webinar    

Boosting Yield and Increasing Quality with Power-Aware Test and Small Delay Defect Testing
Conventional test compression tools create patterns that force the device under test to consume up to ten times more power compared to normal operation, leading to IR drop, overheating, and test program failures. Separately, manufacturing process variations can introduce small delays that adversely affect critical design paths, leading to circuit failures, and expensive silicon returns. These two combined trends effectively increase the cost...
preview: http://www.techonline.com   date: 8/5/2009

webinar    

Choosing the right Multicore software architecture for high performance control and data-plane …
Multicore processors are being broadly adopted in networking applications in order to meet increasingly demanding performance requirements and tight power budgets. While multicore offers a continuation of Moore ’s law on the hardware side, it introduces a disruptive change and therefore a great challenge for software designers. In this webinar Enea will present an overview of various software architectures for control plane and data plane...
preview: https://event.on24.com   date: 11/17/2009

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