
SHARC Processor Evaluation Kit Limited Time Offer
Analog Devices is offering a 50% discount on new SHARC Processor Family evaluation kits until July 31, 2008.
The SHARC Processor fits into a variety of applications such as Digital Home, Pro Audio, Industrial and Instrumentation, Automotive, Military, and Medical.
The following kits will be discounted to $249 through your local Distributor: ADZS-21262-EZLITE, ADZS-21364-EZLITE, ADZS-21369-EZLITE, and ADZS-21375-EZLITE.

| |
-
hot list
 -
Semiconductor datasheets on the Web
A list of links to semiconductor manufacturers, including direct links to their datasheets index page.
Simple but cool.
preview:
http://www.bgs.nu
-
hot list
 -
Semiresources
THE quintessential, exhaustive, most complete Semiconductor manufacturer's list on the web! Author strive to keep it up to date and as the most useful site of it's kind.
If you see areas that are lacking, have comments, ideas or suggestions, author will be happy to entertain them.
preview:
http://www.semiresources.com
-
hot list
 -
VLSI Microprocessors
This page is an index to available datasheets and white papers regarding high performance (RISC and other) microprocessors.
Unfortunately, it is no longer being updated as of late 2000.
Sigh.
preview:
http://www.microprocessor.sscc.ru
-
overview
-
Microprocessor Instruction Set Cards
A number of microprocessor instruction set cards in a common format are available as described in an article entitled A Set of Standard Microprocessor Programming Cards.
preview:
http://archive.comlab.ox.ac.uk
-
resource
 -
Chip Directory
Chip directory, sorted by numerical device number, plus index of chip manufacturers.
One of the better practical resources.
preview:
http://www.xs4all.nl
 |
| 
| 
With PADS® I/O Designer, you can easily create legal FPGA pin assignmentsup to 50% times fasterwith its correct-by-construction, drag and drop functionality.
By reducing design cycle time, I/O Designer accelerates time to market, enabling your company to compete in the ever-changing electronics market.
I/O Designer follows major FPGA vendor rules for correct I/O assignments.
It also eliminates re-spin risk, improves PCB performance, and reduces routing congestion.
View the free demo.
| 
| 
|
|
|