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Conquering the Memory Bandwidth Bottleneck On-Chip
Memory bandwidth challenges are increasing with next-generation high-bandwidth technologies and designers are looking for new cost-effective approaches for resolving bandwidth and efficiency issues on-chip. Today's popular home entertainment and mobile devices require an increasing number of processors that are dependent on sharing the same pipe, which has generated a sizeable efficiency bottleneck for SoC designers and system architects....
preview: http://www.eetimes.com   date: 9/23/2010 |

webinar    

Debugging High Speed Memory and Serial buses with Greater System Visibility
System integration and validation has become more challenging due to greater levels of sophistication and complexity in modern mixed signal designs. This live webinar will focus on the latest tools and techniques for properly verifying analog and digital characteristics of high performance designs. In-depth applications examples will be covered including FPGA debug, high speed serial links and DDR memory testing. Attend this 45 minute...
preview: http://www.eetimes.com   date: 9/21/2010 |

webinar    

Memory Optimization Techniques for High-Speed Video SoCs
DTV manufacturers continue to push for improved picture quality and higher resolution — all with additional features at lower price points. These requirements are driving further integration along with increased bandwidth requirements for DTV SoCs (System-on-a-Chip). This increased SoC complexity necessitates the ability to look at data flows through the system and their impact on memory efficiency. Graphics processors, display...
preview: http://www.techonline.com   date: 4/7/2009 |

webinar    

MEMS Foundry Manufacturing and CMOS integration - Challenges and Solutions
n the past five years we have seen a huge step in the evolution of MEMS applications. Some may even call it a revolution. Traditionally, Inkjet printer heads and automotive applications have dominated MEMS volume production. Today, demand for MEMS is particularly high in the consumer and mobile sector with further applications appearing every day. Part of this MEMS revolution has been the changing requirements for associated ASIC CMOS...
preview: http://www.eetimes.com   date: 10/5/2010 |

webinar    

Solving High-Speed DDR SI and Probing Challenges
The speed of DDR (Double Data Rate) memory technology has increased rapidly in the last few years. The latest DDR3 technology is operating over 1.6GT/s and at the same time, the signal amplitude has decreased to reduce power consumption. With faster and smaller signals, the designs have fewer margins for error, thus having good signal integrity is important to guarantee reliable system operation. On top of that, a huge DDR validation...
preview: http://www.techonline.com   date: 1/13/2009 |

webinar    

Tips to Debug DDR Parametric and Protocol Measurements with an MSO
DDR memory system debug and validation work require debug tools that can provide comprehensive parametric and protocol measurement. Are you looking for an affordable solution that will provide the capability to verify your DDR system? This presentation will review the tips of using a mix signal oscilloscope as a one box solution in making DDR parametric and protocol measurement.
preview: http://www.techonline.com   date: 10/1/2009 |