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book    

Advanced Memory Optimization Techniques for Low-Power Embedded Processors
The design of embedded systems warrants a new perspective because of the following two reasons: Firstly, slow and energy inefficient memory hierarchies have already become the bottleneck of the embedded systems. It is documented in the literature as the memory wall problem. Secondly, the software running on the contemporary embedded devices is becoming increasingly complex. It is also well understood that no silver bullet exists to solve the...
preview: http://www.amazon.com   date: 5/8/2007

book    

DRAM Circuit Design: Fundamental and High-Speed Topics
DRAM Circuit Design, Second Edition brings students and practicing chip designers an easy-to-follow, yet thorough, introductory to the subject. Focusing on the chip designer rather than the end-user, this Second Edition offers expanded, up-to-date coverage of DRAM circuit design by presenting both standard and high-speed implementations. Additionally, it explores a range of topics including: the DRAM array, peripheral circuitry, global...
preview: http://www.amazon.com   date: 12/4/2007

paper    

An Embedded Flexible Content-Addressable Memory Core for Inclusion in a FPGA
This paper describes a novel architecture for a content-addressable memory core which is intended to be included in a Field-Programmable Gate Array or an Embedded Programmable Logic Core. Compared to a standard content-addressable memory, our architecture allows for arbitrary data and tag widths; this flexibility is vital in FPGA applications, since the size of the data and tag fields are not known when the FPGA is manufactured.
preview: http://www.ece.ubc.ca  

paper    

Improving SoC Design Flows with Robust and Precise Embedded Memory Models
Practically all digital System on Chip (SoC) designs contain embedded ROM, RAM, or register file memories of various sizes. These types of embedded memory on average consume 30 - 50 percent of die area and this percentage is growing at an astounding 25 percent annually [1]. With so many designs containing memory devices, on-chip critical timing paths will either start or end at memory address, data, or control pins.
preview: http://www.eda.org   date: 1/1/2002

organization    

Open NAND Flash Interface (ONFI) Working Group
The mission of the ONFI Working Group is to simplify integration of NAND flash memory into consumer electronics (CE) devices and computing platforms. These leading companies are jointly defining an enhanced chip-level standard interface for the attachment of NAND flash memory to host systems.
preview: http://www.onfi.org  

organization    

PISMO™ Advisory Council
A collaboration of industry leading companies with the objective to define and develop standards for Board Level (External) Memory Interfaces and promote their Worldwide Adoption.
preview: http://www.pismoworld.org  

seminar    

New SI Technologies for High-speed Designs Web Seminar
Is your company introducing newer and faster technologies for next-generation designs? This technical seminar will focus on simulation-based signal-integrity analysis of several emerging technologies, including DDR, DDR2, PCI Express, SAS, and SATA. We'll introduce new Mentor design kits and explore the use of HyperLynx software for technology tradeoffs, termination, topology and routing decisions, and routing constraints, including...
preview: http://www.mentor.com   date: 6/24/2008