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webinar    

Advanced Capabilities and Design Interaction with FPGA-Based Prototyping
In order to boost the utility of an FPGA-based prototyping platform, certain critical components are required, including a high-performance, low latency communication channel and direct access to all pins, signals, nodes and registers within the FPGA. In this webcast will discuss how the new advanced use modes and capabilities of the HAPS® High-performance ASIC Prototyping System™ with the new HAPS Universal Multi-Resource Bus Interface...
preview: http://www.eetimes.com   date: 02/24/2011 |

webinar    

EDA Virtual Conference- EDA: The Next Big Things
OpenSystems Media is proud to announce the first EDA Virtual Conference, entitled EDA: The Next Big Things. Engineers from around the world are invited to learn about Analog and Mixed Signal, System-on-Chip, High-Level Design, and Verification. Each session will also include a special 'Ask the Experts' panel for attendees to ask their questions and network with vendors. The fifth and final session of the day is the keynote Executive...
preview: https://event.on24.com   date: 10/14/2010 |

webinar    

EDA, ESL and More Ideas from DAC
Can hardware and software be developed for SoCs independently, or are the two so tightly coupled they must be developed concurrently? Can modeling the 'system' wait until actual silicon is available, or must it be done with better tools at the architecture stage before the SoC is created? If 90% of the world's IP is already available, why is creating SoCs so challenging? When did RTL become an antique? The whole model of a SoC now,...
preview: https://event.on24.com   date: 10/14/2009 |

webinar    

Increase Your Productivity and Profitability: A Deterministic Path to Silicon Realization
The EDA360 vision is transforming the industry. Building on this vision, Cadence introduces a new approach to realizing silicon. In this webinar, we'll show you an innovative, streamlined, and cost-efficient method that enables you to design, implement, and verify your ICs by focusing on three requirements—design intent, abstraction and convergence. Using a mixed-signal design as an example, Cadence will show you a new path combining the...
preview: http://www.eetimes.com   date: 11/2002/2010 |

webinar    

Maximizing Your Investment in the UVM
This webinar, developed by Cadence R&D, will demonstrate the technical aspects of the UVM Reference Flow so that users can immediately employ this new environment to improve their verification productivity. The Universal Verification Methodology (UVM) Reference Flow gives the UVM community a standardized set of design and verification components with which to test and validate their flows. Combined with the recent book, 'A Practical...
preview: http://www.eetimes.com   date: 12/15/2010 |

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