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Express Logic - RTOS, TCP/IP, USB Stack, File System, GUI
Express Logic - RTOS, TCP/IP, USB Stack, File System, GUI
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Mentor Graphics - IC Design.


SHARC Processor Evaluation Kit Limited Time Offer
Analog Devices is offering a 50% discount on new SHARC Processor Family evaluation kits until July 31, 2008. The SHARC Processor fits into a variety of applications such as Digital Home, Pro Audio, Industrial and Instrumentation, Automotive, Military, and Medical. The following kits will be discounted to $249 through your local Distributor: ADZS-21262-EZLITE, ADZS-21364-EZLITE, ADZS-21369-EZLITE, and ADZS-21375-EZLITE.
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webinar   1-5 star rating for this site  
CDNLive! 2007 Webinar Series for Custom Design
Join us for a webinar series that showcases custom design technology presentations from CDNLive! Silicon Valley 2007. Cadence customers and Cadence technologists will discuss the latest challenges in custom design, as well as the technologies and methodologies they've used to help them overcome those challenges. Don't miss this opportunity to see the People's Choice Winners and other valuable content delivered at the conference for the...
Click here to preview in another window preview: http://www.cadence.com   date: 12/11/2007

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webinar   1-5 star rating for this site  
Circuit-Simulation-Driven RF/Analog System-In-Package Design
Today's wireless device manufacturers must continually pack more functionality into less space while striving to meet ever-shrinking market windows. Analog/RF system-in-package (SiP) modules comprise one of the fastest growing integration fabrics in the wireless silicon market. Learn how driving an Analog/RF SiP module implementation from a single top-level schematic (that includes RF/analog chips and IC Package level substrate RF passives)...
Click here to preview in another window preview: http://www.cadence.com   date: 9/6/2007

webinar   1-5 star rating for this site  
Co-simulation with MATLAB®, Simulink®, and HDL Simulators
When implementing a complex design in an ASIC or FPGA, engineers must be satisfied that the hardware implementation will match the system specification. Whether your HDL is written from scratch, automatically generated code, previously-written IP, or a mix of the three, you can use the EDA co-simulation link products from the MathWorks to ensure design correctness. In this webinar you will learn how you can ensure that your HDL...
Click here to preview in another window preview: http://www.techonline.com   date: 12/6/2007

webinar   1-5 star rating for this site  
Improving Analog Layout Productivity
Traditionally custom layout has been a manual and time-consuming process. See how the use of a Unified Constraint System, linked to advanced placement and routing applications, can increase layout productivity dramatically by enabling easy capture of designer intent, through a front-to-back constraint system, which is then used to guide the physical implementation
Click here to preview in another window preview: http://www.cadence.com   date: 3/29/2007

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eSOL’s Multi-core ready RTOS


eSOL’s Multi-core ready RTOS. The eT-Kernel Multi-Core Edition supports two scheduling modes, True SMP Mode (TSM) and Single Processor Mode (SPM). Both provide software developers with a blended multiprocessor RTOS, and the scalability and high throughput efficiency of SMP, with the more deterministic and realtime characteristics of AMP. All this is within a single tightly-coupled multiprocessor solution supporting POSIX 1003.1. 2004.
eSOL’s Multi-core ready RTOS


 

 

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