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Integrated RTOS, communications stacks and middleware
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SHARC Processor Evaluation Kit Limited Time Offer
Analog Devices is offering a 50% discount on new SHARC Processor Family evaluation kits until July 31, 2008. The SHARC Processor fits into a variety of applications such as Digital Home, Pro Audio, Industrial and Instrumentation, Automotive, Military, and Medical. The following kits will be discounted to $249 through your local Distributor: ADZS-21262-EZLITE, ADZS-21364-EZLITE, ADZS-21369-EZLITE, and ADZS-21375-EZLITE.
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book   1-5 star rating for this site  
Reuse Methodology Manual for System-on-a-Chip Designs
Outlines a set of best practices for creating reusable designs for use in an SoC design methodology. These practices are based on the authors' experience in developing reusable designs, as well as the experience of design teams in many companies around the world. Silicon and tool technologies move so quickly that many of the details of design-for-reuse will undoubtedly continue to evolve over time. But the fundamental aspects of the...
Click here to preview in another window preview: http://www.amazon.com  

book   1-5 star rating for this site  
System Level Design Model with Reuse of System IP
System Level Design Model with Reuse of System IP addresses system design by providing a framework for assessing and developing system design practices that observe and utilise reuse of system design know-how. The know-how accumulated in the companies represents an intellectual asset, or property ('IP').
Click here to preview in another window preview: http://www.amazon.com   date: 9/1/2003

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portal   1-5 star rating for this site  
Design and Reuse
The world's largest directory of Virtual Components, Software and Services for designing systems on chip IP exchange on Internet works; test it by getting a free IP and look at the new format of IP Exchanger. Part of the massive Techweb database.
Click here to preview in another window preview: http://www.design-reuse.com  

book-classic   1-5 star rating for this site  
Virtual Components Design and Reuse
Design reuse is not just a topic of research but a real industrial necessity in the microelectronic domain and thus driving the competitiveness of relevant areas like for example telecommunication or automotive. Most companies have already dedicated a department or a central unit that transfer design reuse into reality.
Click here to preview in another window preview: http://www.amazon.com   date: 11/1/2000

paper   1-5 star rating for this site  
A Survey of Digital Design Reuse
The authors survey recent advances in digital design reuse. They stress the need for effective strategies that accommodate reuse throughout the entire design process.
Click here to preview in another window preview: http://horizon.ece.utexas.edu   date: 1/1/2001

webinar   1-5 star rating for this site  
Editorial Webinar: Design re-use, from design to deployment
There's no doubt that the job of the embedded developer is far more challenging than it's been in the recent past. That phenomenon is the result of multiple factors. These include the demand from consumers for more features in less space, faster and more complex microprocessors, the need for more software to run on those newer processors, and design windows that continue to shrink. In this webinar, we will address both the hardware and...
Click here to preview in another window preview: http://www.techonline.com   date: 4/9/2008

eSOL’s Multi-core ready RTOS


eSOL’s Multi-core ready RTOS. The eT-Kernel Multi-Core Edition supports two scheduling modes, True SMP Mode (TSM) and Single Processor Mode (SPM). Both provide software developers with a blended multiprocessor RTOS, and the scalability and high throughput efficiency of SMP, with the more deterministic and realtime characteristics of AMP. All this is within a single tightly-coupled multiprocessor solution supporting POSIX 1003.1. 2004.
eSOL’s Multi-core ready RTOS


 

 

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