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Save 70% on Blackfin Processor Development Tools
For a limited time, March 1 - May 28, ADI is offering two discounted development tools bundles including full VisualDSP++ Development Software and an Emulator. So order your bundle today!

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archive
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Design-for-test Technical Publications
Titles include * Embedded Deterministic Test for Low Cost Manufacturing (ITC 2002) * Reducing Simulation Mismatches in Design-for-Test (DFT) Implementation * TestKompress with EDT Technology: Reducing Time and Expense in Test * Embedded Deterministic Test - DFT Technology for Low-Cost IC Manufacturing Test * Using FastScan Diagnostics to Improve Time-to-Volume
preview:
http://www.mentor.com
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blog
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DFT Digest.com
Hi! My name is John Ford, and I write this blog.
I have been working in this industry for a little over 23 years (gasp!) in various engineering capacities: test (digital and mixed-signal), DFT, verification, and some design automation.
I like doing a variety of things.
The bulk of my career has been in Southern California, for companies such as Western Digital, Silicon Systems, and Texas Instruments.
Just recently I worked for...
preview:
http://www.dftdigest.com
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podcast
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Mentor Graphics EDA Training and Employment Resources for Unemployed Designers
Recently unemployed? Concerned about your EDA technical training? Christine Egli and Tom Floodeen of Mentor Graphics discuss how the company is reaching out to the EDA community to offer technical training in EDA (Electronic Design Automation) to 'displaced workers.' For those who qualify, the program is an excellent way to beef up your technical skills as well as to network with other EDA professionals seeking employment opportunities.
preview:
http://www.eg3.com
date: 3/24/2009

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webinar
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Boosting Yield and Increasing Quality with Power-Aware Test and Small Delay Defect Testing
Conventional test compression tools create patterns that force the device under test to consume up to ten times more power compared to normal operation, leading to IR drop, overheating, and test program failures.
Separately, manufacturing process variations can introduce small delays that adversely affect critical design paths, leading to circuit failures, and expensive silicon returns.
These two combined trends effectively increase the cost...
preview:
http://www.techonline.com
date: 8/5/2009
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