 
Mentor Graphics
View Technical Publication Library
| |
-
webinar
-
Best Practices for Quick Closure of Verilog Designs
When you design ASIC you have to deal with the tangled reset circuits, multiple clock domains, power dissipation, and other complex issues.
In this presentation we will discuss the best design practices for the proper reset circuit, avoiding glitches in cross domain data paths, special consideration for using gated clocks in your design, and some coding techniques for the most efficient verification of the design.
Following these practices...
preview:
http://www.aldec.com
date: 8/14/2008
-
webinar
-
Cut Months and Millions from ASIC Design
Learn about a unique system development method that can dramatically reduce your ASIC-based system design’s time-to-market and total cost.
In this 20-minute webcast, you’ll see how Altera’s ASIC development system provides: In-system, at-speed verification of both hardware and software The lowest risk approach to custom
preview:
http://www.altera.com
date: 7/11/2008
-
webinar
-
Implementing Large and Complex 65-nm ASICs in the Magma Flow
65-nanometer process technology advancements allow us to put more functionality into a single large, complex chip.
As we pack hundreds of millions of transistors into a chip, increased EDA tool performance and integrated design flows are necessary to address all nanometer issues and effects.
In this webinar, Fastrack Design describes the implementation of a high-performance, 65-nm ASIC using the Magma flow.
Synthesis, virtual prototyping,...
preview:
http://www.magma-da.com
date: 11/27/2007
-
personal page
-
ASIC Design For Signal Processing
ASIC is an acronym for Application Specific Integrated Circuit.
It refers to the technology that many chip designers, including Lucent, use for the physical creation of their chips.
This project focuses heavily on the creation of such a design, which will be incorporated as part of one of Bell Lab's future research chips.
preview:
http://www.geoffknagge.com
-
personal page
-
Jeff's ASIC Tools Page
This page contains a number of tools I have written which are useful for ASIC design.
They are written in perl, or ANSI C, and all have the GNU GPL license.
I hope you find them as useful as I do. All I ask is that you drop me a note if you find them helpful.
Verilog tools.
preview:
http://www.kwcpa.com
-
personal page
-
World of ASIC (Personal Page)
There just isn't a great source of detailed VLSI/DIGITAL information out there.
If I actually keep this up, this should be it. However, unless people take an active interest and submit some ideas, tutorials, examples, may be some cores etc., it may die very soon.
preview:
http://www.asic-world.com
 |
